1. Field of the Invention
The present invention relates to a non-volatile semiconductor device which includes non-volatile memory cells and has a high voltage generator for generating a high voltage that is used at the time of data erasure and, particularly, at the time of data writing.
2. Description of the Related Art
EEPROMs are one type of non-volatile semiconductor devices. Of those EEPROMs, a NAND cell type EEPROM comprising a plurality of memory cells connected in series is known as a memory device which can accomplish high integration of memory cells. FIG. 1 illustrates the structure of the memory cell used in this NAND cell type EEPROM. A source 91 and a drain 92 are formed in a semiconductor substrate 90. A floating gate 93 and a control gate 94 are deposited via an insulating film on the substrate 90.
A NAND cell has a plurality of memory cells 95, each shown in FIG. 1, connected in series. More specifically, as shown in FIG. 2, each NAND cell has one end connected via a select gate 96 to a bit line BL and the other end connected via a select gate 97 to a common source line S. A plurality of such memory cells are arranged in a matrix, constituting an EEPROM, with control gates serially connected in a columnar direction, forming a word line WL.
Such a NAND cell type EEPROM functions as follows. Data writing is performed on the memory cells in order, starting from the one located farther away from the bit line BL. With memory cells each constituted of an n channel MOS transistor, a boosted write voltage VPP (about 20 V) is applied to the control gate of a selected memory cell. An intermediate voltage VM (about 10 V) is applied to the control gates and select gates of non-selected memory cells located on the bit line side. In accordance with data, 0 V (e.g., data "0") or the intermediate voltage VM (e.g., data "1") is applied to the bit line. At this time, the voltage on the bit line is sequentially transferred by the non-selected memory cells to reach the drain of the selected memory cell. When write data is "0," a high electric field is applied between the floating gate and the drain of the selected memory cell and tunnel injection of electrons from the drain to the floating gate occurs, shifting the threshold voltage to the positive direction. When write data is "1," the threshold voltage does not change.
Data erasure is performed simultaneously on all the memory cells in the NAND cell. More specifically, 0 V is applied to all the control gates and select gates, and a boosted erase voltage VE (about 20 V) is applied to the p-type well region (not shown) and the n-type substrate. As a result, electrons are discharged from the floating gate into the p-type well region in every memory cell, shifting the threshold voltage to the negative direction.
In reading data,.a reference voltage of 0 V is applied to the control gate of the selected memory cell and a source voltage vcc (e.g., 3.3 V) is applied to the control gates and select gates of the other memory cells. At this time, a sense amplifier (not shown) detects if a current flows through the selected memory cell, thus accomplishing data reading.
In the NAND cell type EEPROM, the aforementioned word line, intermediate voltage VM and erase voltage VE are generated by a high voltage generator which boosts the source voltage vcc (3.3 V) to acquire a high voltage.
The structure of a conventional high voltage generator of this type is illustrated in FIG. 3. This high voltage generator comprises a booster circuit 102, which has an even number of charge pump circuits 101 cascade-connected in multi-stages, and a voltage limiter 103 connected to the last stage of the charge pump circuit in the booster circuit 102.
Each charge pump circuit 101 comprises a MOSFET 104 having a gate and one of its source and drain connected to the source voltage Vcc of 3.3 V, a MOSFET 105 having a gate and one of its source and drain connected to the other one of the source and drain of the MOSFET 104, and a capacitor 106 having one end connected to the other one of the source and drain of the MOSFET 104. The other one of the source and drain of the MOSFET 105 in the preceding stage is connected to one of the source and drain of the MOSFET 105 in the subsequent stage, thus allowing charge pump circuits 101 to be cascade-connected. Two clock signals .phi. 1 and .phi. 2 having different phases as shown in FIG. 4, which are obtained by an oscillation circuit, such as a ring oscillator, are alternately supplied to the other end of the capacitor 106.
The voltage limiter 103 comprises a plurality of Zener diodes (two diodes in this example) connected in series. Assuming that the Zener breakdown voltage VZ per Zener diode is 10 V, the limit voltage of the voltage limiter is 20 V, which is the same as the write voltage VPP and the erase voltage VE, when two Zener diodes are used as shown in FIG. 3, and the limit voltage is 10 V or the intermediate voltage VM when one Zener diode is used.
In writing data in the above-described NAND cell type EEPROM, the higher the write voltage VPP is, the shorter the time required for the data writing becomes. Conventionally, however, this voltage could not be set too high and there is an upper limit for the following reason.
Supposed that VPP is set too high at the time of data writing and the threshold voltage of a memory cell among the series-connected memory cells in a NAND cell is shifted too much in the positive direction. Even if that memory cell is a non-selected memory cell and the source voltage of 3.3 V is applied to its control gate at the time of data reading, this non-selected memory cell will not be turned on, disabling data reading from a selected memory cell. That is, if the write voltage VPP is set too high, overwriting occurs at the time of data writing.
This overwriting may occur by a change in external temperature. Even if 20 V, the normal write voltage, is obtained at one temperature in the high voltage generator with the structure shown in FIG. 3, when the Zener breakdown voltage rises due to a change in external temperature, VPP also rises. Assume that the amount of the shift of the normal threshold voltage has been acquired at the writing speed of, for example, 100 .mu.sec when the write voltage VPP is 20 V. As VPP rises to 23 V, for example, the amount of the shift of the threshold voltage at the writing speed of 100 .mu.sec becomes large.
As a solution to such overwriting, conventionally, an intelligent writing system has been developed. This system raises the write voltage VPP gradually and accomplishes data writing in a plurality of writing actions, not in one action. The intelligent writing system repeats writing data and reading data after data writing. When the read data matches with the written data, this system terminates the writing operation.
As the intelligent writing system should perform data writing a plurality of times, it undesirably needs a longer time to accomplish data writing.
Further, the intelligent writing system requires a comparator, etc. so that its circuit structure inevitably becomes complex.